1. Field of the Invention
The present invention relates to correction techniques for delta sigma converters for audio digital to analog (D/A) and analog to digital (A/D) conversion applications.
2. Description of Prior Art
Delta Sigma D/A and A/D converters have become the standard devices for data conversion in audio applications. The purpose of using Delta Sigma converters in audio applications is to predict and reduce in-band quantization error, which causes distortion, with feedback loops. A good overview of the theory of Delta Sigma data converters is given in the book xe2x80x98Delta Sigma Data Convertersxe2x80x99, by Norsworthy, Schreier, and Temes (IEEE Press, 1997).
U.S. Pat. No. 5,815,102 by the present inventor (incorporated herein by reference) teaches methods for correcting delta sigma quantizers to account for distortion introduced by PWM on the output. In FIG. 1 (taken from that patent), a typical first order delta sigma quantizer is shown. The purpose of this quantizer, in a D/A converter, is to convert a high resolution digital signal having several bits to a single bit representation which can be accurately converted to analog. Most delta sigma digital to analog designs operate in the normal sampled time domain13 that is, with the assumption that all signals are sampled at a fixed frequency f, and the value at each sample represents an impulse response with a finite area and an infinitesimally small width. The invention taught in U.S. Pat. No. 5,815,102 used some generalizations of this assumption to include converters using output signals having variable pulse width. One such application is noise shaped pulse width modulation (PWM).
FIG. 2, also taken from U.S. Pat. 5,815,102 shows a demodulator which might be used in an oversampling D/A converter. High resolution data 202 (for example, 12 to 20 bit data) enter delta sigma converter 204. The sample rate of this data has already been increased from the low clock rate required to code the data to a medium clock rate used to clock the delta sigma converter (interpolation techniques for oversampling data are well understood by experts in this field). The ratio of the low to the medium clock speed is typically 32 (for example, the clock speed might be increased from 16 kHz to 1 MHz). Delta sigma modulator 204 is clocked by medium clock 213 to generate medium resolution data (for example, 2 to 5 bit words). Duty cycle demodulator 208 is clocked by medium clock 213 and high clock 212. The frequency of the high clock is typically a multiple of the medium clock rate (for example, to 16 MHz from 1 MHz). The output of duty cycle demodulator 208 is low resolution data (1 or 2 bit words) at the high clock rate. In this figure, the 0.5 medium clock (clocking at half the rate of the medium clock) is used for alternating output data formats in systems using pulse width modulation. Other systems of this type are described in works by Craven and by Risbo. See, for example, xe2x80x9cToward the 24-bit DAC: Novel Noise-Shaping Topologies Incorporating Correction for the Nonlinearity in a PWM OutPut Stagexe2x80x9d by Peter Craven, J. Audio Eng. Soc., Vol. 41, No., 5, May 1993. See also U.S. Pat. Nos. 5,548,286 and 5,784,017 by Craven. See also WO 97/37433 by L. Risbo et al.
Refer now to FIG. 3, showing a generalization of delta sigma noises haping loops 300. Both the signals Y and U are assumed to be instantaneously sampled discrete time signals. It is desirable to remove that restriction, and to allow either or both Y and U to be signals with real width, and, potentially, varying shape.
The case where feedback signal Y is a generalized signal allows for the use of PWM techniques, as described above, as well as compensation for imperfect pulse shaping and inter-symbol interference. In summary, freeing up the limitations on Y allows for converters that can have arbitrary output waveforms from the final low resolution digital to analog converter. There is a need in the art to develop a systematic approach to the optimization of the feedback and correction coefficients for such a system.
There also remains a need to allow U, the input signal, to be a generalized signal. The case where U is a generalized signal is useful for the conversion of one kind of delta sigma stream into another. An interesting example would be the conversion of a 128 Fs one-bit data stream into a 16-bit Fs six-bit stream. This technique would also be useful in applications requiring sample rate conversion.
Finally, there remains a need for systems in which both signals U and Y are not constrained to be impulse sampled systems. Applications include conversion from a delta sigma format into PWM format, and combinations of sample rate conversion with PWM output.
There is a need in the art to generalize this technique to the case where multiple mutually nonlinear functions (MMNFs) are applied to feedback or feed forward terms before they enter the integrators. Freeing this constraint on higher order delta sigma converter designs can permit the output of arbitrary waveforms from the D/A converter.
An object of the present invention is to provide a means for the design of delta sigma converters using MMNFs. This invention is a generalization of previous work (U.S. Pat. No. 5,815,102), in which multiples of the same nonlinear function are used as adders at different integrators in a higher order delta sigma converter.
A delta sigma modulator using MMNFs is at least a second order delta sigma modulator having at least two feed forward and/or feedback loops, in which two of the functions applied before summation at the integrators are nonlinear and are not simple multiples of each other. Such a modulator might also be used in a system that takes in input data at a rate higher than the modulator rate, or in one where the sample rate is changed in the delta sigma converter.
The present invention includes a method for using roots of the state transition matrix to calculate MMNFs for application as correction terms in a delta sigma modulator. The feedback functions are then optionally fit to polynomials (rather than implemented in lookup tables), which allow a portable representation of the nonlinear functions. In some cases, where the functions modify the average gain of the feedback loop (affecting the frequency response of the modulator), polynomial calculation can be used iteratively to drive the new system""s transfer function toward that of the old loop when a low level signal is applied. This improvement stage can help in high gain or low oversample ratio stages.
A delta sigma modulator according to the present invention is of at least second order, operating at an operating clock rate, and having an input and producing an output in response to the input. It has at least two state variables, a quantizer having an input responsive to one of the state variables and providing a feedback signal and a modulator output signal, two mutually nonlinear function blocks, each applying a nonlinear function to the feedback from the quantizer, to form two mutually nonlinear feedback signals, and two adders for adding one of the nonlinear feedback signals to the input of one of the state variables. The nonlinear functions applied by the function blocks are substantially linear functions when viewed at a clock rate which is a multiple of the operating clock rate.
The nonlinear function blocks may comprise read only memories (look up tables), or blocks for computing powers of the feedback from the quantizer and applying scaling to the powers.
A method according to the present invention for correcting distortion in a delta sigma modulator of at least second order, having at least two state variables responsive to feedback from an output quantizer and operating at an operating clock rate, comprises the steps of determining a system equivalent to the modulator, the system operating at a higher clock rate, the higher clock rate being a multiple of the operating clock rate, wherein the output of the system is substantially linear at the higher clock rate, modeling the response to system operation at the higher clock rate, modelling the correction to be applied to each integrator feedback path at the higher clock rate to correct the modelled distortion, computing the correction to be applied within the modulator at the operating clock rate such that the modulator operating at the operating clock rate substantially matches the operation of the system operating at the higher clock rate in response to the same outputs, and implementing the computed correction by applying at least two mutually nonlinear functions to the feedback from the quantizer, and adding the respective results to at least two state variables.
The step of computing the correction includes the steps of determining the roots of the state transition matrix and computing the mutually nonlinear functions based on the roots.